The circuit is designed to be used in high performance memory-decoding or data-routing applications requiring very short propagation delay times. In highperformance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
Keywords: 4:16 bit decoder design, CMOS inverter, IC 74AC11138, decoder, practical
